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| HM5116400 Series HM5117400 Series 4,194,304-word 4-bit Dynamic RAM ADE-203-648C (Z) Rev. 3.0 Feb. 27, 1997 Description The Hitachi HM5116400 Series, HM5117400 Series are CMOS dynamic RAMs organized 4,194,304-word 4-bit. They employ the most advanced 0.5 m CMOS technology for high performance and low power. The HM5116400 Series, HM5117400 Series offer Fast Page Mode as a high speed access mode. They have package variations of standard 300-mil 26-pin plastic SOJ and standard 300-mil 26-pin plastic TSOP. Features * * * Single 5 V ( 10%) Access time: 50 ns/60 ns/70 ns (max) Power dissipation Active mode : 495 mW/440 mW/385 mW (max) (HM5116400 Series) : 550 mW/495 mW/440 mW (max) (HM5117400 Series) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) Fast page mode capability Long refresh period 4096 refresh cycles : 64 ms (HM5116400 Series) : 128 ms (L-version) 2048 refresh cycles : 32 ms (HM5117400 Series) : 128 ms (L-version) 3 variations of refresh -only refresh -beforerefresh Hidden refresh Battery backup operation (L-version) Test function 16-bit parallel test mode * * * * * HM5116400 Series, HM5117400 Series Ordering Information Type No. HM5116400S-5 HM5116400S-6 HM5116400S-7 HM5116400LS-5 HM5116400LS-6 HM5116400LS-7 HM5117400S-5 HM5117400S-6 HM5117400S-7 HM5117400LS-5 HM5117400LS-6 HM5117400LS-7 HM5116400TS-5 HM5116400TS-6 HM5116400TS-7 HM5116400LTS-5 HM5116400LTS-6 HM5116400LTS-7 HM5117400TS-5 HM5117400TS-6 HM5117400TS-7 HM5117400LTS-5 HM5117400LTS-6 HM5117400LTS-7 Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 300-mil 26-pin plastic TSOP II (TTP-26/24DA) Package 300-mil 26-pin plastic SOJ (CP-26/24DB) 2 HM5116400 Series, HM5117400 Series Pin Arrangement HM5116400S/LS Series HM5116400TS/LTS Series VCC I/O1 I/O2 1 2 3 4 5 26 25 24 23 22 21 VSS I/O4 I/O3 VCC I/O1 I/O2 1 2 3 4 5 26 25 24 23 22 21 VSS I/O4 I/O3 A11 6 A9 A11 6 A9 A10 A0 A1 A2 A3 VCC 8 9 10 11 12 13 19 18 17 16 15 14 (Top view) A8 A7 A6 A5 A4 VSS A10 A0 A1 A2 A3 VCC 8 9 10 11 12 13 19 18 17 16 15 14 (Top view) A8 A7 A6 A5 A4 VSS Pin Description Pin name A0 to A11 Function Address input -- Row/Refresh address A0 to A11 -- Column address A0 to A9 Data input/Data output Row address strobe Column address strobe Write enable Output enable VCC VSS Power supply Ground I/O1 to I/O4 3 HM5116400 Series, HM5117400 Series Pin Arrangement HM5117400S/LS Series HM5117400TS/LTS Series VCC I/O1 I/O2 1 2 3 4 5 26 25 24 23 22 21 VSS I/O4 I/O3 VCC I/O1 I/O2 1 2 3 4 5 26 25 24 23 22 21 VSS I/O4 I/O3 NC 6 A9 NC 6 A9 A10 A0 A1 A2 A3 VCC 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS A10 A0 A1 A2 A3 VCC 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS (Top view) (Top view) Pin Description Pin name A0 to A10 Function Address input -- Row/Refresh address A0 to A10 -- Column address A0 to A10 Data input/Data output Row address strobe Column address strobe Write enable Output enable VCC VSS NC Power supply Ground No connection I/O1 to I/O4 HM5116400 Series, HM5117400 Series Block Diagram (HM5116400 Series) Timing and control A0 A1 to A9 * * * Column address buffers Column decoder 4M array 4M array Row decoder * * * I/O buffers 4M array I/O1 to I/O4 Row address buffers A10 A11 4M array 5 HM5116400 Series, HM5117400 Series Block Diagram (HM5117400 Series) Timing and control A0 A1 to A10 * * * Column address buffers Column decoder 4M array 4M array Row decoder * * * I/O buffers 4M array I/O1 to I/O4 Row address buffers 4M array 6 HM5116400 Series, HM5117400 Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Input high voltage Input low voltage Note: Symbol VCC VIH VIL Min 4.5 2.4 -1.0 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Note 1 1 1 1. All voltage referred to VSS. 7 HM5116400 Series, HM5117400 Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (HM5116400 Series) HM5116400 -5 -6 -- -- -7 Test conditions t RC = min TTL interface , = VIH Dout = High-Z CMOS interface , VCC - 0.2 V Dout = High-Z CMOS interface , VCC - 0.2 V Dout = High-Z t RC = min = VIH = VIL Dout = enable t RC = min t PC = min CMOS interface Dout = High-Z, CBR refresh: tRC = 31.3 s t RAS 0.3 s 0V Vin 7V 0 V Vin 7 V Dout = disable High Iout = -5 mA Low Iout = 4.2 mA -- -- Parameter Operating current* , * 2 1 Symbol I CC1 I CC2 Min Max Min Max Min Max Unit -- -- 90 2 80 2 70 2 mA mA Standby current -- 1 -- 1 -- 1 mA Standby current (L-version) -only refresh current*2 Standby current* 1 I CC2 -- 150 -- 150 -- 150 A I CC3 I CC5 -- -- 90 5 -- -- 80 5 -- -- 70 5 mA mA -beforecurrent refresh I CC6 I CC7 I CC10 -- -- -- 90 80 -- -- 80 70 -- -- 70 60 350 mA mA A Fast page mode current*1, * 3 Battery backup current (Standby with CBR refresh) (L-version) Input leakage current Output leakage current Output high voltage Output low voltage 350 -- 350 -- I LI I LO VOH VOL -10 10 -10 10 2.4 0 -10 10 -10 10 -10 10 -10 10 VCC 0.4 A A V V VCC 2.4 0.4 0 VCC 2.4 0.4 0 Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while = VIL. 3. Address can be changed once or less while = VIH. 8 HM5116400 Series, HM5117400 Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (HM5117400 Series) HM5117400 -5 Parameter Operating current* , * 2 1 -6 100 -- 2 -- -7 Test conditions t RC = min TTL interface , = VIH Dout = High-Z CMOS interface , VCC - 0.2 V Dout = High-Z CMOS interface , VCC - 0.2 V Dout = High-Z t RC = min = VIH = VIL Dout = enable t RC = min t PC = min CMOS interface Dout = High-Z, CBR refresh: tRC = 62.5 s t RAS 0.3 s 0V Vin 7V 0 V Vin 7 V Dout = disable High Iout = -5 mA Low Iout = 4.2 mA -- -- Symbol I CC1 I CC2 Min Max Min Max Min Max Unit -- -- 90 2 80 2 mA mA Standby current -- 1 -- 1 -- 1 mA Standby current (L-version) -only refresh current*2 Standby current* 1 I CC2 -- 150 -- 150 -- 150 A I CC3 I CC5 -- -- 100 -- 5 -- 90 5 -- -- 80 5 mA mA -beforecurrent refresh I CC6 I CC7 I CC10 -- -- -- 100 -- 90 -- 90 80 -- -- 80 70 350 mA mA A Fast page mode current*1, * 3 Battery backup current (Standby with CBR refresh) (L-version) Input leakage current Output leakage current Output high voltage Output low voltage 350 -- 350 -- I LI I LO VOH VOL -10 10 -10 10 2.4 0 -10 10 -10 10 -10 10 -10 10 VCC 0.4 A A V V VCC 2.4 0.4 0 VCC 2.4 0.4 0 Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while = VIL. 3. Address can be changed once or less while = VIH. 9 HM5116400 Series, HM5117400 Series Capacitance (Ta = 25C, VCC = 5 V 10%) Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. = VIH to disable Dout. AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) *1, *2, *18, *19 Test Conditions * * * Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.4 V Output load: 2 TTL gate + C L (100 pF) (Including scope and jig) 10 HM5116400 Series, HM5117400 Series Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5116400/HM5117400 -5 Parameter Random read or write cycle time precharge time precharge time pulse width pulse width Row address setup time Row address hold time Column address setup time Column address hold time to delay time Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT Min 90 30 7 50 13 0 7 0 7 17 12 13 50 5 13 0 0 3 Max -- -- -- -6 Min 110 40 10 Max -- -- -- -7 Min 130 50 10 Max -- -- -- Unit ns ns ns Notes 10000 60 10000 15 -- -- -- -- 37 25 -- -- -- -- -- -- 50 0 10 0 10 20 15 15 60 5 15 0 0 3 10000 70 10000 18 -- -- -- -- 45 30 -- -- -- -- -- -- 50 0 10 0 15 20 15 18 70 5 18 0 0 3 10000 ns 10000 ns -- -- -- -- 52 35 -- -- -- -- -- -- 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4 to column address delay time hold time hold time to precharge time to Din delay time delay time from Din delay time from Din Transition time (rise and fall) 11 HM5116400 Series, HM5117400 Series Read Cycle HM5116400/HM5117400 -5 Parameter Access time from Access time from Access time from address Access time from Read command setup time Read command hold time to Read command hold time to Column address to Column address to to output in low-Z Output data hold time Output data hold time from Output buffer turn-off time Output buffer turn-off to to Din delay time lead time lead time Symbol t RAC t CAC t AA t OEA t RCS t RCH t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD Min -- -- -- -- 0 0 0 25 25 0 3 3 -- -- 13 Max 50 13 25 13 -- -- -- -- -- -- -- -- 13 13 -- -6 Min -- -- -- -- 0 0 0 30 30 0 3 3 -- -- 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- 15 15 -- -7 Min -- -- -- -- 0 0 0 35 35 0 3 3 -- -- 18 Max 70 18 35 18 -- -- -- -- -- -- -- -- 15 15 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12 12 Notes 8, 9, 20 9, 10, 17, 20 9, 11, 17, 20 9, 20 Write Cycle HM5116400/HM5117400 -5 Parameter Write command setup time Write command hold time Write command pulse width Write command to Write command to Data-in setup time Data-in hold time lead time lead time Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 7 7 13 13 0 7 Max -- -- -- -- -- -- -- -6 Min 0 10 10 15 15 0 10 Max -- -- -- -- -- -- -- -7 Min 0 15 10 18 18 0 15 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14 12 HM5116400 Series, HM5117400 Series Read-Modify-Write Cycle HM5116400/HM5117400 -5 Parameter Read-modify-write cycle time to to delay time delay time delay time Symbol t RWC t RWD t CWD t AWD t OEH Min 131 73 36 48 13 Max -- -- -- -- -- -6 Min 155 85 40 55 15 Max -- -- -- -- -- -7 Min 181 98 46 63 18 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes Column address to hold time from Refresh Cycle HM5116400/HM5117400 -5 Parameter Symbol Min 5 7 0 7 5 Max -- -- -- -- -- -6 Min 5 10 0 10 5 Max -- -- -- -- -- -7 Min 5 10 0 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns Notes setup time (CBR refresh cycle) t CSR hold time (CBR refresh cycle) t CHR setup time (CBR refresh cycle) t WRP hold time (CBR refresh cycle) precharge to hold time t WRH t RPC Fast Page Mode Cycle HM5116400/HM5117400 -5 Parameter Fast page mode cycle time Fast page mode Access time from hold time from pulse width precharge Symbol t PC t RASP t CPA Min Max 35 -- -- 30 -- -6 Min Max 40 -- 35 -- -7 Min Max 45 -- 40 -- Unit ns 16 9, 17, 20 Notes 100000 -- 30 -- 100000 -- 35 -- 100000 ns 40 -- ns ns precharge t CPRH 13 HM5116400 Series, HM5117400 Series Fast Page Mode Read-Modify-Write Cycle HM5116400/HM5117400 -5 Parameter Fast page mode read-modify-write cycle time delay time from Symbol t PRWC Min 76 53 Max -- -- -6 Min 85 60 Max -- -- -7 Min 96 68 Max -- -- Unit ns ns 14 Notes precharge t CPW Test Mode Cycle *19 HM5116400/HM5117400 -5 Parameter Test mode Test mode setup time hold time Symbol t WTS t WTH Min 0 7 Max -- -- -6 Min 0 10 Max -- -- -7 Min 0 10 Max -- -- Unit ns ns Notes Refresh (HM5116400 Series) Parameter Refresh Refresh (L-version) Symbol t REF t REF Max 64 128 Unit ms ms Notes 4096 cycles 4096 cycles Refresh (HM5117400 Series) Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 32 128 Unit ms ms Notes 2048 cycles 2048 cycles 14 HM5116400 Series, HM5117400 Series Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing -only refresh or -beforerefresh). If the internal refresh counter is used, a minimum of eight -beforerefresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + t AA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + t AA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS, t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. leading edge in early write cycles and to leading 15. These parameters are referred to edge in delayed write or read-modify-write cycles. 16. t RASP defines pulse width in Fast page mode cycles. 17. Access time is determined by the longest among t AA, t CAC and t CPA. 18. In delayed write or read-modify-write cycles, must disable output buffer prior to applying data to the device. 19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M 4 are don't care during test mode. Test mode is set by performing a -and-before(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode, perform either a regular beforerefresh cycle or -only refresh cycle. 20. In a test mode read cycle, the value of tRAC , t AA, t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 15 HM5116400 Series, HM5117400 Series 21. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. +16 HM5116400 Series, HM5117400 Series Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing -only refresh or -beforerefresh). If the internal refresh counter is used, a minimum of eight -beforerefresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + t AA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + t AA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS, t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. leading edge in early write cycles and to leading 15. These parameters are referred to edge in delayed write or read-modify-write cycles. 16. t RASP defines pulse width in Fast page mode cycles. 17. Access time is determined by the longest among t AA, t CAC and t CPA. 18. In delayed write or read-modify-write cycles, must disable output buffer prior to applying data to the device. 19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M 4 are don't care during test mode. Test mode is set by performing a -and-before(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode, perform either a regular beforerefresh cycle or -only refresh cycle. 20. In a test mode read cycle, the value of tRAC , t AA, t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 15 HM5116400 Series, HM5117400 Series Early Write Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Address Row Column t WCS t WCH WE t DS t DH Din Din Dout High-Z* * t WCS t WCS (min) 18 HM5116400 Series, HM5117400 Series Delayed Write Cycle*18 t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Address Row Column t CWL t RCS t RWL t WP WE t DZC t DS t DH Din High-Z Din t OEH t OED t DZO OE t OEZ t CLZ High-Z Invalid Dout Dout 19 HM5116400 Series, HM5117400 Series Read-Modify-Write Cycle*18 t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR t RAH t ASC t CAH Address Row t RCS Column t CWD t AWD t RWD t CWL t RWL t WP WE t DZC t DS Din High-Z Din t DH t DZO t OED t OEA t OEH OE t CAC t AA t RAC t OEZ t OHO High-Z Dout t CLZ Dout 20 HM5116400 Series, HM5117400 Series -Only Refresh Cycle t RC t RAS t RP tT t CRP t RPC t CRP t ASR Address t OFF Row t RAH Dout High-Z 21 HM5116400 Series, HM5117400 Series -BeforeRefresh Cycle t RC t RP t RAS t RP t RPC t CSR tT t CHR t RPC t CRP t CP t WRP t WRH t CP Address t OFF Dout High-Z 22 HM5116400 Series, HM5117400 Series Hidden Refresh Cycle t RC t RAS t RP t RC t RAS t RC t RP t RAS t RP RAS tT t RSH t RCD CAS t RAD t ASR t RAH Address Row t ASC t RAL t CAH t CHR t CRP Column t WRP t RCS t RRH t WRH t WRP t WRH WE t DZC High-Z Din t CDD t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout t OED t OEZ t OHO t OFF t OH 23 HM5116400 Series, HM5117400 Series Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t CSH t RCD CAS t RAL t CAL t ASC t CAH Column N t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t RAD t ASR t RAH Address Row t CAL t ASC t CAH Column 1 t CAL t ASC t CAH Column 2 t RCS t RCS WE t DZC t CDD Din t DZO High-Z t OED t DZC t CDD High-Z t DZO t OED t RCH t RCH t RCS t RRH t RCH t DZC t CDD High-Z t DZO t OED OE t RAC t AA t OEA t CAC t CLZ Dout Dout 1 t OH t CPA t AA t OHO t OEA t CPA t AA t OHO t OFF t OEZ Dout 2 t OEA t CAC t CLZ Dout N t OFF t OEZ t OH t OH t OHO t OFF t CAC t OEZ t CLZ 24 HM5116400 Series, HM5117400 Series Fast Page Mode Early Write Cycle t RASP t RP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address ROW Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS t DH t DS t DH t DS t DH Din Din 1 Din 2 Din N Dout High-Z* * t WCS t WCS (min) 25 HM5116400 Series, HM5117400 Series Fast Page Mode Delayed Write Cycle*18 t RASP t RP RAS tT t CSH t RCD CAS t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED t OEH OE Din 1 t DZO t OED t OEH t WP t DZC t DS t DH Din 2 t DZO t OED t OEH t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t CLZ t OEZ Dout Invalid Dout t CLZ t OEZ t CLZ t OEZ High-Z Invalid Dout Invalid Dout 26 HM5116400 Series, HM5117400 Series Fast Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t CP t RCD CAS t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO t OED t OEH OE t OHO t AA t OEA t CAC t AA t CPA t OEZ t OEA t CAC t OHO t AA t CPA t OEZ t OEA t CAC t OHO Din 1 t DZO t OED t OEH t WP t DZC t DS t DH Din 2 t DZO t OED t OEH t WP t DZC t DS t DH Din N t RCS t CWL t ASC t CAH Column 2 t CPW t AWD t CWD t RCS t CWL t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL t CAS t CAS t PRWC t CP t RSH t CAS t CRP Address t RAC t CLZ Dout Dout 1 t CLZ t CLZ t OEZ High-Z Dout 2 Dout N 27 HM5116400 Series, HM5117400 Series Test Mode Cycle*19 Set Cycle** Test Mode Cycle *,** Reset Cycle Normal Mode RAS CAS WE * CBR or RAS-only refresh ** Address, Din, OE: H or L 28 HM5116400 Series, HM5117400 Series Test Mode Set Cycle t RC t RP t RAS t RP RAS t RPC t CSR tT CAS t CP t WTS t WTH t CP t CHR t RPC t CRP WE Address t OFF High-Z Dout 29 HM5116400 Series, HM5117400 Series Package Dimensions HM5116400S/LS Series HM5117400S/LS Series (CP-26/24DB) Unit: mm 26 16.90 17.27 Max 21 19 14 1 68 0.74 13 1.30 Max 0.43 0.10 0.41 0.08 1.27 6.71 0.25 Hitachi Code JEDEC Code EIAJ Code Weight CP-26/24DB MO-077-AA SC-632-A 0.8 g 2.54 0.10 30 HM5116400 Series, HM5117400 Series HM5116400TS/LTS Series HM5117400TS/LTS Series (TTP-26/24DA) Unit: mm 26 17.14 17.54 Max 21 19 14 1 0.42 0.40 0.08 0.06 68 1.27 0.21 M 1.15 Max 2.54 0.10 13 0.80 9.22 0.20 0-5 0.50 0.10 Hitachi Code JEDEC Code EIAJ Code Weight TTP-26/24DA MO-132AB -- 0.30 g 31 HM5116400 Series, HM5117400 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 32 HM5116400 Series, HM5117400 Series Revision Record Rev. 1.0 2.0 Date Oct. 14, 1996 Nov. 14, 1996 Contents of Modification Initial issue Addition of HM5116400-5 Series Addition of HM5117400-5 Series Power dissipation (active) 605/550 mW(max) to 550/495/440 mW (max) (HM5117400 Series) DC Characteristics (HM5117400 Series) I CC1 max: 110/100 mA to 100/90/80 mA I CC3 max: 110/100 mA to 100/90/80 mA I CC6 max: 110/100 mA to 100/90/80 mA 3.0 Feb. 27, 1997 AC Characteristics t RRH min: 5/5/5 ns to 0/0/0 ns Drawn by Y. Kasama Y. Kasama Approved by M. Mishima Y. Matsuno 33 |
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